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AvnetCore: Datasheet
G704-E1 Framer
MC-ACT-ETHCTRL reset_n
Version 1.0, July 2006
Intended Use:
tx_en tx_er txd col crs tx_clk rx_en
Reset
-- ISDN Terminal Equipment -- E2 Interface (multi G704 on chip) -- E1-ATM Interface
AHB Bus Master Lite
AHB Master Bus
MAC Control Layer
AHB Master
TX FIFO
MAC
RX FIFO
rxd rx_clk rx_dv rx_er mdc md_drv_n md_dout md_din
Features:
-- G704 framing de-framing on E1 carriers -- Basic & multi frame alignment -- Alarm bit processing -- Customizable error counters -- Selectable conditions for loss of sync -- CRC4 error checking and monitoring -- Fully synchronous
AHB Slave Bus
AHB Slave
Serial Management Interface Config/ Control
int_rx_frame int_bus_error int_mac_paused int_phy_status_changed
Interrupts
int_tx_frame
Ext Address Check
MII
rx_ext_addr_check_match dest_addr_avbl src_addr_avbl len_type_avbl rx_shift_reg
load_ebl sda_in
Serial I/F
Targeted Devices:
-- SX-A Family -- Axcelerator(R) Family -- ProASICPLUS(R) Family
Block Diagram
Core Deliverables:
-- Netlist Version > Netlist compatible with the Actel Designer place and route tool -- RTL Version > VHDL Source Code > Test Bench -- All > User Guide
The MC-ACT-G704E1 Framer core is designed to handle synchronous frame structures (Recommendation G.704) running on an E1 carrier. Transmitter and receiver part are two completely independent blocks both capable of handling basic and multi frames. Both perform functions such as overhead bit insertion / detection, CRC4 computation and check. A very flexible synchronization unit (Recommendation G.706) synchronizes automatically or by means of an external frame sync signal. The frame builder unit can be configured which of the overhead bits are to be inserted or not. Avnet Memec cores are designed with the philosophy that no global elements should be embedded within the core itself. Global elements include any of the following components: STARTUP, STARTBUF, BSCAN, READBACK, Global Buffers, Fast Output Primitives, IOB Elements, Clock Delay Components, and any of the Oscillator Macros. Avnet Memec cores contain resources present in only the sequential and combinatorial array. This is done to allow flexibility in using the cores with other logic. For instance, if a global clock buffer is embedded within the core, but some external logic also requires that same clock, then an additional global buffer would have to be used. In any instance, where one of our cores generates a clock, that signal is brought out of the core, run through a global buffer, and then brought back into the core. This philosophy allows external logic to use that clock without using another global buffer. A result of this philosophy is that the cores are not self-contained. External logic must be connected to the core in order to complete it.
Synthesis and Simulation Support:
-- Synthesis: Synplicity(R) -- Simulation: ModelSim(R) -- Other tools supported upon request
Verification:
-- Test Bench
Functional Description
TRANSMITTER The transmitter part consists of the multi frame overhead handler and the frame builder itself. Multi Frame Overhead Handler This block is responsible for providing the overhead bits according to the current frame type. These bits are then forwarded to the frame builder unit that inserts them into the outgoing data stream. Frame Builder The frame builder performs all the tasks necessary to output a valid frame that complies with the E1 carrier system. Basic Frame Synchronizer Generator This block synchronizes the incoming data and provides a basic frame reference signal that identifies every bit within a basic frame. Multi Frame Generator The multi frame generator builds a multi frame reference signal based on the basic frame reference and provides the associated interrupts. TS0 Bit Insertion This unit automatically inserts all the special bits on the fly into time slot 0. It uses the frame reference signal to insert the corresponding bits. It inserts the basic frame alignment, the CRC4 multi frame alignment signal, the computed CRC4 value plus the configured special bits. CRC4 Calculation This block computes the CRC4 value on the outgoing data stream and feeds it back to the TS0 bit insertion block. RECEIVER The receiver part comprises the synchronizer block and the analyzer block. Snychronizer The synchronizer samples the incoming data frame and generates the corresponding frame reference signal and the necessary interrupts. Basic Frame Aligner This block synchronizes the incoming data and provides a basic frame reference signal that identifies every bit within a basic frame. Multi Frame Aligner The multi frame aligner detects multi frame structures and builds a multi frame reference signal based on the basic frame reference and provides the associated interrupts. CRC4 Checker This unit computes the CRC4 on the incoming frame and compares it with the received CRC bits and provides the corresponding status signals. Analyzer This unit uses the frame reference signal to analyze the incoming frame. Alarm Detector This unit samples the alarm bits of the incoming frame. It registers them and outputs an alarm history. Plus it marks the reception of the alarm indication signal. Monitor Counter The monitor counter holds error counters that keep track on the CRC4, FAS and E-bit errors that have been detected on the incoming frames. TS0 Signal Capture This block samples the bits in time slot 0 and stores them into a register bank for further processing. The register bank can hold the TS0 bits of 8 consecutive frames within a multi frame structure. AISLOS Detector This unit detects the alarm indication signal (AIS) and the 2Mbit loss condition.
Family SX-A ProASICPLUS Axcelerator
Device COMB SX32A-3 APA150-STD AX500-3 760 (42%) n/a 695 (13%)
Utilization SEQ 510 (48%) n/a 507 (19%) Total 1270 (44%) 2212 (36%) 1202 (15%)
Performance 77 MHz 42 MHz 79 MHz
Verification and Compliance
Complete functional and timing simulation has been performed on the G704-E1 Framer using ModelSim 5.5d. This core has also been used successfully in customer designs.
Signal Descriptions
The following signal descriptions define the IO signals. Signal ClkSys resn CfgFSync.SyncMode[1:0] Direction Input Input Input Description System clock: This is the only clock source for the whole G704-E1 core Asynchronous System Reset: active low Configuration of Frame Synchronizer: "00": transparent (no FSync generated) "01": free run (generate dummy FSync) "10": use external FSync "11": fully automatic sync (G.706) User controlled resync: When toggled form `0' to `1', a resync is initialized Automatic resync after loss of sync: `1': Automatic resync ON ( `0': OFF ) `0': Improved BasicFrame alignment disabled `1': Use improved BasicFrame alignment procedure as in $4.1.1 of G.704/Note 1 (check FA bit 2 of nFAS frames) `0': MultiFrame alignment search disabled (only Basic-Frame search) `1': MultiFrame alignment search enabled Input Input `0': use parallel BFA search (G.706) `1': reuse primary BFA search (PTT simplified search path) `0': MultiFrame alignment loss checking process disabled `1': MultiFrame alignment checking process enabled (if 3 consecutive MFA not found while MFSyncState = InSync, then MFSyncState <= Hunt) `0': CRC4 Error limit of <= 915 disabled `1': CRC4 Error limit checking enabled `0': CRC4 Error counter enabled `1': CRC4 Error counter disabled `0': FAS Error counter enabled `1': FAS Error counter disabled `0': E-Bit counter enabled `1': E-Bit counter disabled E1 / Si of FAS frame E2 / Si of non FAS frame A-Bit Insert enable pattern related to Sa bits Sa4...Sa8 bits Note: When FrameRef.MF.MFSyncState NOT = InSync, then only SaBitsMF(1) will be inserted. `0': CRC4 MultiFrame Mode disabled `1': CRC4 MultiFrame Mode enabled "0x": transparent, "10": synchronize BFA phase, "11": generate BFA phase (Note: when NOT transparent, a new MultiFrame is generated) Output Output Output Output Pulse @ `1' when entering state InSync Pulse @ `1' when leaving state InSync Pulse @ `1' when entering state InSync Pulse @ `1' at begin of each MultiFrame
CfgFSync.ForceResync CfgFSync.AutoResync CfgFSync.FAImprove_411
Input Input Input
CfgFSync.MF_Mode CfgFSync.MF_SyncMode CfgFSync.MFA_Check
CfgFSync.CRC4_Mode CfgFan.CRC_CountEbl CfgFan.FAS_Count_Ebl CfgFan.E_Count_Ebl CfgOverhead.Si_E1 CfgOverhead.Si_E2 CfgOverhead.A-Bit CfgOverhead.InsertEbl[4:0] CfgOverhead.saBitsMF[1:8][4:0]
Input Input Input Input Input Input Input Input Input
CfgFBuild.CRC4_MFMode CfgFBuild.BuildMode[1:0] IntSrc_FSync.BFA.Sync IntSrc_FSync.BFA.SyncLoss IntSrc_FSync.MFA.SyncEntry IntSrc_FSync.MFA.MFSync
Input
IntSrc_FSync.MFA.SyncLoss IntSrc_Fan.AlarmByteCaptured IntSrc_Fan.A_Bit_detected IntSrc_FSync.BFB.Sync IntSrc_FSync.BFB.SyncLoss IntSrc_FSync.MFB.SyncEntry IntSrc_FSync.MFB.MFSync Status_FAn.LOS_2M Status_FAn.AIS Status_FAn.TS0Data Status_FAn.AlarmHistory Status_FAn.ErrorCountCRC[7:0] Status_FAn.ErrorCountFAS[7:0] Status_FAn.ErrorCountE[7:0] SampleCmds.SampleCRC SampleCmds.SampleFAS SampleCmds.SampleE Data_in_FSC.Data Data_in_FSC.DataEbl Data_in_FSC.FSync DiFramed.Data DiFramed.DataEbl DiFrameRef.BF.BitNr[2:0] DiFrameRef.BF.TSNr[4:0] DiFrameRef.BF.BFNr DiFrameRef.BF.BFSyncState[1:0] DiFrameRef.BF.TSInd DiFrameRef.BF.TS0Ind_BF1 DiFrameRef.BF.TS0Ind_BF2 DiFrameRef.BF.FSync DiFrameRef.MF.FrameNr[3:0] DiFrameRef.MF.SMFInd DiFrameRef.MF.MFInd DiFrameRef.MF.SMFSync DiFrameRef.MF.next_MFSync DiFrameRef.MF.MFSync Do_FSC.Data Do_FSC.DataEbl Do_FSC.FSync DataOut_FSC.Data DataOut_FSC.DataEbl DataOut_FrameRef[24:0]
Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input Input Input Input Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input Input Output Output Output
Pulse @ `1' when leaving state InSync Pulse @ `1' when 8 A-bits have been captured (only when BFSyncState = InSync and MFSyncState /= InSync ) Pulse @ `1' when A-Bit sequence "001" has been received Pulse @ `1' when entering state InSync Pulse @ `1' when leaving state InSync Pulse @ `1' when entering state InSync Pulse @ `1' at begin of each MultiFrame 2MBit Loss detection AIS detection result TS0 Data, OTHERS => `0' when not InSync Sampled history of last 8 A-bits Sampled state of CRC error counter Sampled state of FAS/nFAS error counter Sampled state of E-Bit counter Active `1' during one clock cycle, when up write access has been detected to the read-only port of the related counter Active `1' during one clock cycle, when up write access has been detected to the read-only port of the related counter Active `1' during one clock cycle, when up write access has been detected to the read-only port of the related counter Binary NRZ data Data enable (FSC) Frame Sync pulse Binary NRZ Data, synchronized to local clock domain Data enable Frame reference pointer identifying every bit in a frame: Bit number within time slot 1 .. 8 Time slot number 0 .. 31 Basic frame number Basic Frame synchronization state: "01": Hunt, "00": Recover, "10": InSync, "11": OutOFSync Time slot indicator `1' when bit number = 7 Time slot 0 indicator of basic frame 1 Time slot 0 indicator of basic frame 2 `1' when 1st bit of a frame when BFSyncState = InSync Multi frame synchronization state: "00": Hunt, "01": Recover, "10": ParRecover, "11": InSync Sub multi frame indicator `1' at last bit of previous sub multi frame Multi frame indicator `1' at 1st bit of sub multi frame when MFSyncState = InSync `1' one bit before MFSync `1' at 1st bit of multi frame when MFSyncState = InSync Binary NRZ data Data enable (FSC) Frame Sync pulse Binary NRZ Data, synchronized to local clock domain Data enable Frame reference pointer (see DiFrameRef)
Table 2: Core I/O Signals
Recommended Design Experience
For the source version, users should be familiar with HDL entry and Actel design flows. Users should be familiar with Actel Libero v2.2 Integrated Design Environment (IDE) and preferably with Synplify and ModelSim.
Ordering Information
The CORE is provided under license from Avnet Memec for use in Actel programmable logic devices. Please contact Avnet Memec for pricing and more information. Information furnished by Avnet Memec is believed to be accurate and reliable. Avnet Memec reserves the right to change specifications detailed in this data sheet at any time without notice, in order to improve reliability, function or design, and assumes no responsibility for any errors within this document. Avnet Memec does not make any commitment to update this information. Avnet Memec assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction, if such be made, nor does the Company assume responsibility for the functioning of undescribed features or parameters. Avnet Memec will not assume any liability for the accuracy or correctness of any support or assistance provided to a user. Avnet Memec does not represent that products described herein are free from patent infringement or from any other third-party right. No license is granted by implication or otherwise under any patent or patent rights of Avnet Memec. AvnetCore products are not intended for use in life support appliances, devices, or systems. Use of a AvnetCore product in such application without the written consent of the appropriate Memec Design officer is prohibited. All trademarks, registered trademarks, or service marks are property of their respective owners.
Contact Information:
North America 10805 Rancho Bernardo Road Suite 100 San Diego, California 92127 United States of America TEL: +1 858 385 7500 FAX: +1 858 385 7770 Europe, Middle East & Africa Mattenstrasse 6a CH-2555 Brugg BE Switzerland TEL: +41 0 32 374 32 00 FAX: +41 0 32 374 32 01
Ordering Information:
Part Number MC-ACT-G704E1-NET MC-ACT-G704E1-VHD Hardware Actel Core Netlist Actel Core VHDL Resale Contact for pricing Contact for pricing
www.em.avnet.com/actel
Copyright (c) 2006 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other brands are the property of their respective owners. AEM-MC-ACT-G704e1-DS v.1.0-July 2006

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